From the point of view of reliability and power consumption, it is desirable to operate integrated circuit memory devices using lower supply voltages. Accordingly, many memory devices employ down converters for producing reduced supply voltages from a higher voltage source. A typical down converter generates an internal supply voltage by stepping down an external supply voltage of 5 V to a lower level. Such a down converter typically also regulates the reduced supply voltage to increase immunity to variation in the external supply voltage.
FIG. 1 is a schematic block diagram of a memory device incorporating a conventional voltage down converter 3. The conventional voltage down converter 3 includes a PMOS transistor 5 that receives an external supply voltage Vext at a first terminal, and produces a regulated voltage Vint responsive to a control signal generated by a comparator 7 that compares the regulated voltage Vint with a reference voltage Vref.
The regulated voltage Vint generated by the voltage down converter 3 is typically supplied to various circuits of the memory device, including circuits that exhibit current demand that varies responsive to control signals thereto. A write driver circuit, for example, may exhibit increased current demand responsive to a transition write enable signal. This increased demand may momentarily reduce the regulated voltage Vint. However, the reduction in the regulated voltage Vint is fed back to the comparator 7, which responsively lowers the gate voltage applied to the PMOS transistor 5 and drives the regulated voltage Vint up to the reference voltage Vref. Similarly, if the regulated supply voltage Vint goes higher than the reference voltage Vref, the output voltage of the comparator 7 increases and the gate voltage of the PMOS transistor 5 is increased to drive the regulated voltage Vint down to the reference voltage Vref.
However, the down converter 3 typically exhibits a delay in response to fluctuations of the regulated voltage Vint, due to parasitic resistance and parasitic capacitance. This delay can result in significant excursions in the regulated voltage Vint, particularly when a lot of data is read out or written during a high speed memory operation, when multiple write drivers operate simultaneously. If a write operation occurs before the regulated voltage Vint returns to its desired level, the operation of the memory device may be degraded.